

module top();

reg[8:0] ti;
reg[8:0] tj;

wire clk;

always @(posedge clk) begin
	// i=j;
	for(ti=tj; ti>10; ti++) begin
		tj = tj+1;
		
	end 
end



	// `define INST_FIFO_ALL        194:0	// one complete inst_fifo entry
	// 	`define INST_FIFO_GID_SPLIT  194        // DW producer and SW consume forced gid split
	// 	`define INST_FIFO_FUSED_RTAG 193:187    // 7 bit rtag info for the Fused Parent: This is to re-order the AES pkt
	// 	`define INST_FIFO_FUSEDPARENT 186   // indicate if a instruction is the parent of a pair of fused instructions
	// 	`define INST_FIFO_WFEWFI_HLT 185        // indicate if a WFE or WFI is active without a pending event/interrupt. This means core will enter halt
	// 	`define INST_FIFO_SP_ALGN_EXC   184
	// 	`define INST_FIFO_ALGN_EXC   183
	// 	`define INST_FIFO_STG2_EXC   182
	// 	`define INST_FIFO_PWR_CYC    181
	// 	`define INST_FIFO_OPC_VLD    180
	// 	`define INST_FIFO_GRPIDXING  179
	// 	`define INST_FIFO_IFU_PCALGN_ABT_PEND     178
	// 	`define INST_FIFO_LB_END     177
	// 	`define INST_FIFO_LB_START   176
	// 	`define INST_FIFO_LB_VALID   175
	// 	`define INST_FIFO_STREX      174	// 1 bit indicating strex
	// 	`define INST_FIFO_ITBITS     173:166    // itbits just before this instruction
	// 	`define INST_FIFO_GID_WRAP   165	// the gid wrap bit
	// 	`define INST_FIFO_GID        164:159	// the 6 bit gid (without wrap bit)
	// 	`define INST_FIFO_GID_FULL   165:159	// the full 7-bit gid
	// 	`define INST_FIFO_EXC_FULL   158:151
	// 	`define INST_FIFO_EXC_TYP    158:152
	// 	`define INST_FIFO_EXC_EN     151
	// 	`define INST_FIFO_SPW_CNT    150:143	// 8 bits, the number of spw results expected
	// 	`define INST_FIFO_AES_CNT    142:135	// 8 bits, the number of aes results expected
	// 	`define INST_FIFO_PSR_CNT    134:127	// 8 bits, the number of psr results expected
	// 	`define INST_FIFO_NMOP       126:123	// 4 bits, total Number of Memory Ops:Max is 15 from LDM/STM
	// 	`define INST_FIFO_MSIZE      122:120	// 3 bits, total memory size in bytes of this uop
	// 	`define INST_FIFO_ESIZE      119:117	// 3 bits, ld/st element size in bytes
	// 	`define INST_FIFO_ST_BYTES   116:109	// 8 bits, the number of str bytes expected
	// 	`define INST_FIFO_LD_BYTES   108:101	// 8 bits, the number of lod bytes expected
	// 	`define INST_FIFO_ISIZE      100 	// 32 bit opcode, one bit tbit, one bit size
	// 	`define INST_FIFO_TBIT       99 	// 32 bit opcode, one bit tbit, one bit size
	// 	`define INST_FIFO_OPCODE     98:67     // 32 bit opcode, one bit tbit, one bit size
	// 	`define INST_FIFO_OPCODE_HW2 98:83     // opcode hw2 - needed for opcode coverage
	// 	`define INST_FIFO_OPCODE_HW1 82:67     // opcode hw1 - needed for opcode coverage
	// 	`define INST_FIFO_IA         66:3      // 63-bit inst addr
	// 	`define INST_FIFO_COMMITTED  2		// one bit status
	// 	`define INST_FIFO_COMPLETE   1		// one bit status
	// 	`define INST_FIFO_VLD        0		// one bit status
	// 	`define LOAD_FIFO_WIDTH      380
	// 	`define LOAD_FIFO_ALL        379:0
	// 	`define LOAD_FIFO_VA_VLD     379        // 1 bit va valid bit(core tb mostly)
	// 	`define LOAD_FIFO_2ND_PA     378:334    // 45 bit PA
	// 	`define LOAD_FIFO_2ND_ATTR   333:321    // 13 bit attr
	// 	`define LOAD_FIFO_UNALIGNED  320        // 1 bit, ccfail flag
	// 	`define LOAD_FIFO_CCFAIL     319        // 1 bit, ccfail flag
	// 	`define LOAD_FIFO_SEXT       318        // 1 bit, load SExt bit
	// 	`define LOAD_FIFO_DW         317        // 1 bit, DW bit
	// 	`define LOAD_FIFO_INSTR      316:308    // 9 bits, entry in inst_fifo
	// 	`define LOAD_FIFO_GID_WRAP   307        // 1 bit, gid wrap
	// 	`define LOAD_FIFO_GID        306:301    // 6 bits, gid w/o wrap bit
	// 	`define LOAD_FIFO_GID_FULL   307:301    // 7 bits, gid (may not need)
	// 	`define LOAD_FIFO_ATTR       300:288    // 13 bits, page attr
	// 	`define LOAD_FIFO_RESY_DATA  287:224    // 64 bits, dsty data
	// 	`define LOAD_FIFO_DSTY_DVLD  223        // 1 bit tag valid
	// 	`define LOAD_FIFO_DSTY_VLD   222        // 1 bit tag valid
	// 	`define LOAD_FIFO_DSTY_RTAG  221:215    // 7 bits tag of dsty
	// 	`define LOAD_FIFO_DSTY_ATAG  214:207    // 8 bits tag of dsty
	// 	`define LOAD_FIFO_DSTY_TYPE  206:204    // 3 bits type of dsty
	// 	`define LOAD_FIFO_RESX_DATA  203:140    // 64 bits, dstx data
	// 	`define LOAD_FIFO_DSTX_DVLD  139        // 1 bit, tag valid
	// 	`define LOAD_FIFO_DSTX_VLD   138        // 1 bit, tag valid
	// 	`define LOAD_FIFO_DSTX_RTAG  137:131    // 7 bits, tag of dstx
	// 	`define LOAD_FIFO_DSTX_ATAG  130:123    // 8 bits, tag of dstx
	// 	`define LOAD_FIFO_DSTX_TYPE  122:120    // 3 bits, type of dstx
	// 	`define LOAD_FIFO_PA         119:75     // 45 bits, PA of load
	// 	`define LOAD_FIFO_VA         74:11      // 64 bits, VA of load
	// 	`define LOAD_FIFO_LD_SIZE    10:3       // 8 bits, size of load (bytes)
	// 	`define LOAD_FIFO_COMMITTED  2          // 1 bit, instr group was committed
	// 	`define LOAD_FIFO_HAVE_ATTR  1          // 1 bit, got VA,PA,attr
	// 	`define LOAD_FIFO_VLD        0          // 1 bit, entry valid
	// 	parameter INST_FIFO_SIZE=512;
	// 	reg [`INST_FIFO_ALL] inst_fifo[INST_FIFO_SIZE];
	// 	reg [`INST_FIFO_ALL] inst_fifo_flushed;
	// 	reg [`LOAD_FIFO_ALL] load_fifo[INST_FIFO_SIZE];
	// 	reg [1:0] load_fifo_e[INST_FIFO_SIZE];
	// 	`define IMP_DABT_FIFO_WIDTH      46
	// 	`define IMP_DABT_FIFO_ALL        45:0
	// 	`define IMP_DABT_FIFO_PA         45:1    // 45 bit PA
	// 	`define IMP_DABT_FIFO_VLD        0       // 1 bit valid bit
		// wirel2_cpu_dext_err_r2;
		// wirel2_cpu_dvalid_r1;
		// wire[2:0] l2_cpu_dbufid_r1;
		// wire[44:0] fb0_pa;
		// wire[44:0] fb1_pa;
		// wire[44:0] fb2_pa;
		// wire[44:0] fb3_pa;
		// wire[44:0] fb4_pa;
		// wire[44:0] fb5_pa;
		// reg[511:0] opc_buf;
		// reg[511:0] spw_buf;
		reg [8:0]   inst_fifo_rd_ptr;
		reg [8:0]   inst_fifo_wr_ptr;
		// reg [8:0]   load_fifo_rd_ptr;
		// reg [8:0]   load_fifo_wr_ptr;
		reg [8:0]  i;
		reg [9:0]  j;
		// reg [8:0] inst_fifo_wr_ptr_plus1;
		// reg [8:0] load_fifo_wr_ptr_plus1;
		// reg [4:0] st_va_fifo_wr_ptr_plus1;
		// reg        gid_end_bit;
		// reg [8:0]  ld_size;
		// reg   [`XM_AES_RTAG_INDEX-1:0]   lsu_resx_tag_w2;
		// reg           lsu_resx_tag_vld_w2;
		// reg           lsu_resx_dw_w2;
		// reg           lsu_resx_data_cancel_w2;
		// reg   [`XM_AES_RTAG_INDEX-1:0]   lsu_resy_tag_w2;
		// reg           lsu_resy_tag_vld_w2;
		// reg           lsu_resy_dw_w2;
		// reg           lsu_resy_data_cancel_w2;
		// reg   [44:0]  ls_pa_ld_w2;
		// reg   [44:0]  ls_pa_ld_w3;
		// reg   [63:0]  ls_va_ld_w0;
		// reg   [63:0]  ls_va_ld_w1;
		// reg   [63:0]  ls_va_ld_w2;
		// reg   [63:0]  ls_va_ld_w3;
		// reg   [12:0]  ls_attr_ld_w2;
		// reg   [12:0]  ls_attr_ld_w3;
		// reg           sext_ld_w2;
		// reg           big_endian_ld_w2;
		// reg   [2:0]   element_size_ld_w2;
		// reg           unal_second_ld_w2;
		// reg           unal_second_ld_e4;
		// reg           ld_res_matched;
		// reg           ld_resx_matched;
		// reg           ld_resy_matched;
		// reg   [8:0]   ld_res_matched_entry;
		// reg  [63:0]   ls_resx_data_swizzled_w2;
		// reg  [63:0]   ls_resy_data_swizzled_w2;
		// reg           spo_read_par_e2;
		// reg           spo_read_par_w0;
		// reg           spo_read_par_w1;
		// reg           spo_read_par_w2;


// wire       sp_uop_vld_i1;
// 	wire       sp_uop_ns_i1;
// 	wire[37:0] sp_uop_ctl_i1;
// 	wire[63:0] sp_uop_wdata_i1;
// 	wire       sp_resolved_ccpass_i1;
// 	wire       sp_sync_done_i1;
// 	wire       sp_uop_vld_p3;
// 	wire[6:0]  sp_uop_gid_p3;
// 	wire       sp_wfi_p3_q;
	// wire       sp_wfe_p3_q;


	// wire       sp_wfi_p3_q;
	// wire       sp_wfe_p3_q;
	// wire       wfi_wakeup_active;
	// wire       wfe_wakeup_active;

		wire  ck_gclkcr;
		// wire reset;


always @(posedge clk) begin
	// i=j;
	for(ti=tj; ti>10; ti++) begin
		tj = tj+1;
		
	end 
end

always @(posedge ck_gclkcr) begin
	// if(reset) begin
	// 	// fusion_opc_fifo_rd_ptr = 0;
	// 	// fusion_opc_fifo_wr_ptr = 0;
	// 	// opc_fifo_rd_ptr = 0;
	// 	// opc_fifo_wr_ptr = 0;
	// 	// in_preamble = 1'b0;
	// 	// skip_preamble = 1'b0;
	// 	// inst_fifo_rd_ptr = 0;
	// 	// inst_fifo_wr_ptr = 0;
	// 	// load_fifo_rd_ptr = 0;
	// 	// load_fifo_wr_ptr = 0;
	// 	// ld_res_matched        = 0;
	// 	// ld_res_matched_entry  = 0;
	// 	for(j=0;j<INST_FIFO_SIZE;j++) begin
	// 		inst_fifo[j] = 0;
	// 		load_fifo[j] = 0;
	// 		load_fifo_e[j] = 0;
	// 	end
	// end
	// else begin
	// 	if(sp_uop_vld_p3 && (sp_wfi_p3_q || sp_wfe_p3_q))begin
	// for(i=j; i>10; i++) begin
	// j=j+1;
	// i = inst_fifo_rd_ptr;
			for(i=0; i!=10; i++) begin
				// if(inst_fifo[i][`INST_FIFO_GID_FULL] == sp_uop_gid_p3) begin
				// 	inst_fifo[i][`INST_FIFO_WFEWFI_HLT] = (sp_wfi_p3_q & ~wfi_wakeup_active) | (sp_wfe_p3_q & ~wfe_wakeup_active);
				// end
			end
	// 	end
	// end
end


endmodule